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The correct answer is EPROM.
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An EPROM (rarely EROM), or erasable programmable read-only memory, is a type of programmable read-only memory (PROM) chip that retains its data when its power supply is switched off. Computer memory that can retrieve stored data after a power supply has been turned off and back on is called non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. Once programmed, an EPROM can be erased by exposing it to strong ultraviolet light source (such as from a mercury-vapor lamp). EPROMs are easily recognizable by the transparent fused quartz (or on later models resin) window on the top of the package, through which the silicon chip is visible, and which permits exposure to ultraviolet light during erasing.[2] OperationDevelopment of the EPROM memory cell started with investigation of faulty integrated circuits where the gate connections of transistors had broken. Stored charge on these isolated gates changes their threshold voltage. Following the invention of the MOSFET (metal-oxide-semiconductor field-effect transistor) by Mohamed Atalla and Dawon Kahng at Bell Labs, presented in 1960, Frank Wanlass studied MOSFET structures in the early 1960s. In 1963, he noted the movement of charge through oxide onto a gate. While he did not pursue it, this idea would later become the basis for EPROM technology.[3] In 1967, Dawon Kahng and Simon Min Sze at Bell Labs proposed that the floating gate of a MOSFET could be used for the cell of a reprogrammable ROM (read-only memory).[4] Building on this concept, Dov Frohman of Intel invented EPROM in 1971,[4] and was awarded U.S. Patent 3,660,819 in 1972. Frohman designed the Intel 1702, a 2048-bit EPROM, which was announced by Intel in 1971.[4] Each storage location of an EPROM consists of a single field-effect transistor. Each field-effect transistor consists of a channel in the semiconductor body of the device. Source and drain contacts are made to regions at the end of the channel. An insulating layer of oxide is grown over the channel, then a conductive (silicon or aluminum) gate electrode is deposited, and a further thick layer of oxide is deposited over the gate electrode. The floating-gate electrode has no connections to other parts of the integrated circuit and is completely insulated by the surrounding layers of oxide. A control gate electrode is deposited and further oxide covers it.[5] To retrieve data from the EPROM, the address represented by the values at the address pins of the EPROM is decoded and used to connect one word (usually an 8-bit byte) of storage to the output buffer amplifiers. Each bit of the word is a 1 or 0, depending on the storage transistor being switched on or off, conducting or non-conducting. The switching state of the field-effect transistor is controlled by the voltage on the control gate of the transistor. Presence of a voltage on this gate creates a conductive channel in the transistor, switching it on. In effect, the stored charge on the floating gate allows the threshold voltage of the transistor to be programmed. Storing data in the memory requires selecting a given address and applying a higher voltage to the transistors. This creates an avalanche discharge of electrons, which have enough energy to pass through the insulating oxide layer and accumulate on the gate electrode. When the high voltage is removed, the electrons are trapped on the electrode.[6] Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades. The programming process is not electrically reversible. To erase the data stored in the array of transistors, ultraviolet light is directed onto the die. Photons of the UV light cause ionization within the silicon oxide, which allows the stored charge on the floating gate to dissipate. Since the whole memory array is exposed, all the memory is erased at the same time. The process takes several minutes for UV lamps of convenient sizes; sunlight would erase a chip in weeks, and indoor fluorescent lighting over several years.[7] Generally, the EPROMs must be removed from equipment to be erased, since it is not usually practical to build in a UV lamp to erase parts in-circuit. Electrically Erasable Programmable Read-Only Memory (EEPROM) was developed to provide an electrical erase function and has now mostly displaced ultraviolet-erased parts. DetailsAs the quartz window is expensive to make, OTP (one-time programmable) chips were introduced; here, the die is mounted in an opaque package so it cannot be erased after programming – this also eliminates the need to test the erase function, further reducing cost. OTP versions of both EPROMs and EPROM-based microcontrollers are manufactured. However, OTP EPROM (whether separate or part of a larger chip) is being increasingly replaced by EEPROM for small sizes, where the cell cost isn't too important, and flash for larger sizes. A programmed EPROM retains its data for a minimum of ten to twenty years,[8] with many still retaining data after 35 or more years, and can be read an unlimited number of times without affecting the lifetime. The erasing window must be kept covered with an opaque label to prevent accidental erasure by the UV found in sunlight or camera flashes. Old PC BIOS chips were often EPROMs, and the erasing window was often covered with an adhesive label containing the BIOS publisher's name, the BIOS revision, and a copyright notice. Often this label was foil-backed to ensure its opacity to UV. Erasure of the EPROM begins to occur with wavelengths shorter than 400 nm. Exposure time for sunlight of one week or three years for room fluorescent lighting may cause erasure. The recommended erasure procedure is exposure to UV light at 253.7 nm of at least 15 Ws/cm2, usually achieved in 20 to 30 minutes with the lamp at a distance of about 2.5 cm.[9] Erasure can also be accomplished with X-rays:
EPROMs have a limited but large number of erase cycles; the silicon dioxide around the gates accumulates damage from each cycle, making the chip unreliable after several thousand cycles. EPROM programming is slow compared to other forms of memory. Because higher-density parts have little exposed oxide between the layers of interconnects and gate, ultraviolet erasing becomes less practical for very large memories. Even dust inside the package can prevent some cells from being erased.[12] ApplicationFor large volumes of parts (thousands of pieces or more), mask-programmed ROMs are the lowest cost devices to produce. However, these require many weeks lead time to make, since the artwork for an IC mask layer must be altered to store data on the ROMs. Initially, it was thought that the EPROM would be too expensive for mass production use and that it would be confined to development only. It was soon found that small-volume production was economical with EPROM parts, particularly when the advantage of rapid upgrades of firmware was considered. Some microcontrollers, from before the era of EEPROMs and flash memory, use an on-chip EPROM to store their program. Such microcontrollers include some versions of the Intel 8048, the Freescale 68HC11, and the "C" versions of the PIC microcontroller. Like EPROM chips, such microcontrollers came in windowed (expensive) versions that were used for debugging and program development. The same chip came in (somewhat cheaper) opaque OTP packages for production. Leaving the die of such a chip exposed to light can also change behavior in unexpected ways when moving from a windowed part used for development to a non-windowed part for production. EPROM generations, sizes and typesThe first generation 1702 devices were fabricated with the p-MOS technology. They were powered with VCC = VBB = +5 V and VDD = VGG = -9 V in Read mode, and with VDD = VGG = -47 V in Programming mode.[13][14] The second generation 2704/2708 devices switched to n-MOS technology and to three-rail VCC = +5 V, VBB = -5 V, VDD = +12 V power supply with VPP = 12 V and a +25 V pulse in Programming mode. The n-MOS technology evolution introduced single-rail VCC = +5 V power supply and single VPP = +25 V[15] programming voltage without pulse in the third generation. The unneeded VBB and VDD pins were reused for additional address bits allowing larger capacities (2716/2732) in the same 24-pin package, and even larger capacities with larger packages. Later the decreased cost of the CMOS technology allowed the same devices to be fabricated using it, adding the letter "C" to the device numbers (27xx(x) are n-MOS and 27Cxx(x) are CMOS). While parts of the same size from different manufacturers are compatible in read mode, different manufacturers added different and sometimes multiple programming modes leading to subtle differences in the programming process. This prompted larger capacity devices to introduce a "signature mode", allowing the manufacturer and device to be identified by the EPROM programmer. It was implemented by forcing +12 V on pin A9 and reading out two bytes of data. However, as this was not universal, programmer software also would allow manual setting of the manufacturer and device type of the chip to ensure proper programming.[16]
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1T-SRAM is a pseudo-static random-access memory (PSRAM) technology introduced by MoSys, Inc., which offers a high-density alternative to traditional static random-access memory (SRAM) in embedded memory applications. Mosys uses a single-transistor storage cell (bit cell) like dynamic random-access memory (DRAM), but surrounds the bit cell with control circuitry that makes the memory functionally equivalent to SRAM (the controller hides all DRAM-specific operations such as precharging and refresh). 1T-SRAM (and PSRAM in general) has a standard single-cycle SRAM interface and appears to the surrounding logic just as an SRAM would. Due to its one-transistor bit cell, 1T-SRAM is smaller than conventional (six-transistor, or "6T") SRAM, and closer in size and density to embedded DRAM (eDRAM). At the same time, 1T-SRAM has performance comparable to SRAM at multi-megabit densities, uses less power than eDRAM and is manufactured in a standard CMOS logic process like conventional SRAM. MoSys markets 1T-SRAM as physical IP for embedded (on-die) use in System-on-a-chip (SOC) applications. It is available on a variety of foundry processes, including Chartered, SMIC, TSMC, and UMC. Some engineers use the terms 1T-SRAM and "embedded DRAM" interchangeably, as some foundries provide MoSys's 1T-SRAM as "eDRAM". However, other foundries provide 1T-SRAM as a distinct offering. Technology1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 kilobits in total) coupled to a bank-sized SRAM cache and an intelligent controller. Although space-inefficient compared to regular DRAM, the short word lines allow much higher speeds, so the array can do a full sense and precharge (RAS cycle) per access, providing high-speed random access. Each access is to one bank, allowing unused banks to be refreshed at the same time. Additionally, each row read out of the active bank is copied to the bank-sized SRAM cache. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed. There have been four generations of 1T-SRAM: Original 1T-SRAM About half the size of 6T-SRAM, less than half the power. 1T-SRAM-M Variant with lower standby power consumption, for applications such as cell phones. 1T-SRAM-R Incorporates ECC for lower soft error rates. To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that. 1T-SRAM-Q This "quad-density" version uses a slightly non-standard fabrication process to produce a smaller folded capacitor, allowing the memory size to be halved again over 1T-SRAM-R. This does add slightly to wafer production costs, but does not interfere with logic transistor fabrication the way conventional DRAM capacitor construction does.Comparison with other embedded memory technologies1T-SRAM has speed comparable to 6T-SRAM (at multi-megabit densities). It is significantly faster speed than eDRAM, and the "quad-density" variant is only slightly larger (10–15% is claimed). On most foundry processes, designs with eDRAM require additional (and costly) masks and processing steps, offsetting the cost of a larger 1T-SRAM die. Also, some of those steps require very high temperatures and must take place after the logic transistors are formed, possibly damaging them. 1T-SRAM is also available in device (IC) form. The Nintendo GameCube was the first video game system to use 1T-SRAM as a primary (main) memory storage; the GameCube possesses several dedicated 1T-SRAM devices. 1T-SRAM is also used in the successor to the GameCube, Nintendo's Wii console. Note that this is not the same as 1T DRAM, which is a "capacitorless" DRAM cell built using the parasitic channel capacitor of SOI transistors rather than a discrete capacitor. MoSys claims the following sizes for 1T-SRAM arrays:
See alsoUS Patent 7,146,454 "Hiding refresh in 1T-SRAM Architecture"* (by Cypress Semiconductor) describes a similar system for hiding DRAM refresh using an SRAM cache. References
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Which type of memory chip can be erased only when it is removed from the computer and exposed to a special type of ultraviolet light?
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